DRAMS and SRAMS are used extensively in computer memories. Each DRAM cell is composed of a transistor, such as a metal oxide semiconductor field effect transistor (MOSFET), and a capacitor. Static random access memories (SRAMS) are based on a larger cell comprised of several transistors and capacitors.
Circuit designers focus on methods of device layouts which can increase device density and circuit speed. As techniques and tools are developed to handle larger wafers for improved yield, several design strategies have emerged.
One of these strategies disclosed in prior art is that memory cells can be achieved with high integration by forming word lines that lie between the source and drain regions and capacitors which use one of the source and drain regions as a storage node electrode. Also, the bit lines are buried in the semiconductor substrate and are electrically connected to the source or drain regions. However, the active area containing the MOSFET arrays is defined by a combination of the isolation regions and buried bit lines troughs. Overlay errors between the isolation mask and the buried bit lines mask result in a variation in the width of the buried bit lines conductors which increases the likelihood that bit lines opens will occur. A more serious result is that the alignment tolerances between these mask levels create a leakage path between two adjacent capacitor contact diffusions. Yet another concern associated with this design is that overlay errors between a buried bit line and isolation masks results in a variation in the dimensions of the active areas containing the transistors. This variation in active area leads to variation in electrical characteristics and reduced process yield. These defects in the cell design can render it inoperable.
A second strategy disclosed in prior art relies on a layout in which bit lines are not recessed beneath the upper surface of the silicon. This forces a pattern of conductive segments which must be wired with separate word lines conductors. Therefore, word lines and bit lines compete for the same space which results in a loss of surface area and a decrease in the packing density.
To write in and to read out information stored as bits in individual cells it is necessary to form orthogonal arrays of word lines and bit lines. Word lines and bit lines are connected to the gate and drain, respectively, of the transistor of each memory cell. One popular type of capacitor used in DRAMS is the “stacked capacitor” which is fabricated over a top surface of a semiconductor substrate. The source of the transistor of each memory cell is connected to a capacitor storage node of a stacked capacitor. The output terminals, the drains and sources, of an n-channel field effect transistor reverse function as current flow through the transistor reverses. For example, during a write of a logical “1” into a memory cell having an n-channel transistor and a stored logical “0”, the output terminal of the transistor coupled to the bit line is the drain and the output terminal coupled to the capacitor is the source. During a read operation, with a “1” stored in the memory cell, the output terminal of the transistor coupled to the capacitor is the drain and the other output terminal coupled to the bit line is the source.
Stacked capacitors are popular because the capacitance can be increased as the overlapping area of the capacitor plates is increased., and the process complexity associated with deep trench processing is avoided.
Previous problems have been encountered when a via is used to make contact to a stacked capacitor. As a result of etching the via, the design line width of the bit lines can be effected. With design ground rules of <0.25 um today and moving toward 0.10 um in the not too distant future, any process step which effects the line width will raise serious questions of device reliability and manufacturability.
Another problem occurs when processing sequences in the formation of the transistors lead to the need for a deep contact hole. This leads to an increase in the distance from the bit lines to the surface of the semiconductor body which can result in poor filing of a contact hole. Poor contact hole filing can cause reliability problems as result of and lead to contact failures.
It is desirable to reduce many of these problems and provide an efficient structure which defines active areas of a semiconductor substrate in which circuits and/or memory cells can be formed.